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Webinar : Accelerating Semiconductor Processes Control

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Webinar : Accelerating Semiconductor Processes Control
05 Dec

Webinar : Accelerating Semiconductor Processes Control

Tuesday 17 December

            Auckland (NZDT) : 10:00pm
            Brisbane (AEST) : 7:00pm
            Sydney, Canberra, Melbourne, Hobart (AEDT) : 8:00pm
            Adelaide (ACDT) : 7:30pm
            Perth (AWST) : 5:00pm

Register

Recent advances in 3D Optical Metrology accelerate in-line quality control for both front and back end processes. In this webinar, Bruker present case studies that address improving yield, identifying root cause  failure and driving next generation device development from bare wafer to final packaged device.

Bruker will highlight requirements for advanced telecommunication, compact on-board electronics, and electric vehicles covering metrology needs for denser interconnect networks, finer redistribution layer (RDL), direct wafer to wafer bonding and wafer fan-out packaging.

Front end (FEOL) examples will include:

  • Wafer bin roughness and edge roll-off
  • CMP efficiency full die flatness
  • CD metrology including TSV, deep trench RIE (Bosch process)
  • Epi layer defect quantification in high power devices


Back end (BEOL) and packaging examples will address:

  • Under Bump Metallisation (UBM)
  • Recess defect inspection
  • Full die screening for dense interconnect control

Speaker: Samuel Lesko, Senior Manager for Optical and Tribology Applications, Bruker Nano Surfaces Division