The new CG792 from Stanford Research Systems extends precision clock synthesis capabilities with up to four independent ultra-low jitter outputs from 1 mHz to 2.2 GHz. Reliable, low-jitter clocks help maintain signal integrity in systems using high-speed ADCs and DACs and other applications, minimising artifacts caused by jitter and modulation.
In communications systems and networks, jitter, wander, or frequency offsets can lead to high bit error rates or total loss of synchronisation. The CG792 provides exceptionally clean, stable clocks required for the most critical applications while setting new standards for frequency accuracy, phase noise performance, and operational flexibility.
At the heart of the CG792 lies a sophisticated dual analog PLL architecture utilising state-of-the-art reference synthesiser phase locked loops. This design employs intelligent spur avoidance algorithms that automatically select optimal reference frequencies to eliminate integer boundary spurs. The system automatically chooses between several precision reference frequencies to maximise phase detector frequency while minimizing spurious content, maintaining decimal frequency resolution with seamless frequency transitions.
